TPS2490
TPS2491
www.ti.com
SLVS503D NOVEMBER 2003REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and
voltage range, V
TIMER
= 0 V, and all outputs unloaded; typical specifications are at T
J
= 25癈, V
VCC
= 48 V, V
TIMER
= 0 V, and
all outputs unloaded; positive currents are into pins.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SUPPLY CURRENT (VCC)
Enabled
V
EN
= Hi, V
SENSE
= V
OUT
= V
VCC
450 1000
礎
Disabled
V
EN
= Lo, V
SENSE
= V
VCC
= V
OUT
90
250
礎
CURRENT SENSE INPUT (SENSE)
I
SENSE
Input bias current
V
SENSE
= V
VCC
, V
OUT
= V
VCC
7.5
20
礎
REFERENCE VOLTAGE OUTPUT (VREF)
V
REF
Reference voltage
0 < I
VREF
< 1 mA
3.9
4
4.1
V
POWER LIMITING INPUT (PROG)
Input bias current, device enabled, sourcing or
I
PROG
0 < V
PROG
< 4 V, V
EN
= 48 V
5
礎
sinking
R
PROG
Pulldown resistance, device disabled
I
PROG
= 200 礎, V
EN
= 0 V
375
600
&
POWER LIMITING AND CURRENT LIMITING (SENSE)
Current sense threshold V
(VCC-SENSE)
with
V
PROG
= 2.4 V, V
OUT
= 0 V or
V
CL
17
25
33 mV
power limiting trip
V
PROG
= 0.9 V, V
OUT
= 30 V, V
VCC
= 48 V
V
SENSE
Current sense threshold V
(VCC-SENSE)
without
V
PROG
= 4 V, V
SENSE
= V
OUT
45
50
55 mV
power limiting trip
V
PROG
= 4 V, V
OUT
= V
SENSE
,
t
F_TRIP
Large overload response time to GATE low
V
(VCC-SENSE)
: 0 ?200 mV,
1.2
祍
C
(GATE-OUT)
= 2 nF, V
(GATE-OUT)
= 1 V
TIMER OPERATION (TIMER)
V
TIMER
= 0 V
15.0
25.0
34.0
礎
Charge current (sourcing)
V
TIMER
= 0 V, T
J
= 25癈
20.0
25.0
30.0
礎
V
TIMER
= 5 V
1.50
2.5
3.70
礎
Discharge current (sinking)
V
TIMER
= 5 V, T
J
= 25癈
2.10
2.5
3.10
礎
TIMER upper threshold voltage
3.9
4
4.1
V
TIMER lower reset threshold voltage
TPS2491 only
0.96
1.0
1.04
V
D
RETRY
Fault retry duty cycle
TPS2491 only
0.5% 0.75% 1.0%
GATE DRIVE OUTPUT (GATE)
V
SENSE
= V
VCC
, V
(GATE-OUT)
= 7 V,
I
GATE
GATE sourcing current
15
22
35
礎
V
EN
= Hi
V
EN
= Lo, V
GATE
= V
VCC
1.8
2.4
2.8 mA
GATE sinking current
V
EN
= Hi, V
GATE
= V
VCC
,
75
125
250 mA
V
(VCC-SENSE)
e 200 mV
GATE output voltage, V
(GATE-OUT)
12
16
V
Propagation delay: EN going true to GATE
V
EN
= 0 ?2.5 V, 50% of V
EN
to 50% of
t
D_ON
25
40
祍
output high
V
GATE
, V
OUT
= V
VCC
, R
(GATE-OUT)
= 1 M&
V
EN
= 2.5 V ?0, 50% of V
EN
to 50% of
Propagation delay: EN going false (0 V) to
t
D_OFF
V
GATE
, V
OUT
= V
VCC
,
0.5
1
祍
GATE output low
R
(GATE-OUT)
= 1 M&, t
FALL
< 0.1 祍
V
TIMER
: 0 ?5 V, t
RISE
< 0.1 祍, 50% of
Propagation delay: TIMER expires to GATE
V
TIMER
to 50% of V
GATE
, V
OUT
= V
VCC
,
0.8
1
祍
output low
R
(GATE-OUT)
= 1 M&,
Copyright ?20032012, Texas Instruments Incorporated
3
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